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| AS1702 - AS1705 1.8W Single-Channel Audio Power Amplifiers D a ta S he e t 1 General Description The AS1702 - AS1705 are single-channel differential audio power-amplifiers designed to drive 4 and 8 loads. The integrated gain circuitry of these amplifiers and their small size make them ideal for 2.7- to 5V-powered portable audio devices. The differential input design improves noise rejection and provides common-mode rejection. A bridge-tied load (BTL) design minimizes external component count, while providing high-fidelity audio power amplification. The devices deliver 1.8W continuous average power per channel to a 4 load with less than 1% total harmonic distortion (plus noise), while operating from a single 2.7 to 5V supply. For reduced component designs, the devices are available with different gain levels as shown in Table 1. Table 1. Standard Products Model AS1702 AS1703 AS1704 AS1705 Gain Adjustable (via external components) AV = 0dB AV = 3dB AV = 6dB 2 Key Features ! 2.7 to 5.5V (VCC) Single-Supply Operation THD+N: 1.8W into 4 at 1% (per Channel) Differential Input Adjustable Gain Option (AS1702) Internal Fixed Gain to Reduce External Component Count (AS1703, AS1704, AS1705) <100nA Low-Power Shutdown Mode Click and Pop Suppression Pin-Compatible to National Semiconductor LM4895 (AS1705) and Maxim MAX9718A/B/C/D Operating Temperature Range: -40 to +85C Package Types - 10-pin MSOP - 10-pin DFN ! ! ! ! ! ! ! ! Integrated shutdown circuitry disables the bias generator and amplifiers, and reduces quiescent current consumption to less than 100nA. The shutdown input can be set active-high or active-low. All devices contain clickand-pop suppression circuitry that reduces audible clicks and pops during power-up and shutdown. The AS1702 - AS1705 are pin compatible with the LM4895 and the MAX9718A/B/C/D. The devices are available in a 10-pin MSOP package and a 10-pin DFN package. Figure 1. Simplified Block Diagram ! 3 Applications The devices are ideal as audio front-ends for battery powered audio devices such as MP3 and CD players, mobile phones, PDAs, portable DVD players, and any other hand-held battery-powered device. Single Supply 2.7 to 5.5V 9 VCC 4 IN+ 2 IN1 SHDN 3 SHDM - + 10 OUT+ RL = 4 or 8 6 OUT- AS1702/AS1703/ AS1704/AS1705 7 GND www.austriamicrosystems.com Revision 1.47 1 - 20 AS1702 - AS1705 Data Sheet - P i n o u t 4 Pinout Pin Assignments Figure 2. Pin Assignments (Top View) SHDN 1 2 10 9 OUT+ SHDN 1 2 10 OUT+ 9 INSHDM 3 IN+ 4 AS1702/ AS1703/ AS1704/ AS1705 VCC N/C INSHDM 8 3 7 GND IN+ 4 AS1702V/ AS1703V/ AS1704V/ AS1705V VCC N/C 8 7 GND BIAS 5 10-pin MSOP Package 6 OUT- BIAS 5 10-pin DFN Package 6 OUT- Pin Descriptions Table 2. Pin Descriptions - MSOP-10 and TDFN-10 Package Pin 1 2 3 4 5 6 7 8 9 10 Name SHDN INSHDM IN+ BIAS OUTGND N/C VCC OUT+ Inverting Input Shutdown-Mode Polarity Input. This pin controls the polarity of pin SHDN. Connect this pin high for an active-high SHDN input. Connect this pin low for an active-low SHDN input (see Table 6 on page 11). Non-Inverting Input DC Bias Bypass Bridge Amplifier Negative Output Ground Not Connected. No internal connection. Power Supply Bridge Amplifier Positive Output Description Shutdown Input. The polarity of this pin is dependent on the state of pin SHDM. www.austriamicrosystems.com Revision 1.47 2 - 20 AS1702 - AS1705 Data Sheet - A b s o l u t e Maximum Ratings 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter Supply Voltage (VCC to GND) Any Other Pin to GND Input Current (Latchup Immunity) Continuous Power Dissipation (TAMB = +70C) (TAMB = +25C) Min -0.3 -0.3 -50 Max +7 VCC + 0.3 50 600 1,000 1 Unit V V mA mW mW kV C C Comments JEDEC 17 MSOP-10 MSOP-10 Human Body Model and MIL-Std883E 3015.7 methods Continuous Power Dissipation Electro-Static Discharge (ESD) Operating Temperature Range (TAMB) Storage Temperature Range -40 -65 +85 +150 Package Body Temperature +260 C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices" Using PCB metal plane and thermally-conductive paste. www.austriamicrosystems.com Revision 1.47 3 - 20 AS1702 - AS1705 Data Sheet - E l e c t r i c a l Characteristics 6 Electrical Characteristics 5V Operation Table 4. Electrical Characteristics - 5V Supply, TAMB = +25C (unless otherwise specified) Symbol VCC ICC ISHDN VIH VIL VBIAS Parameter Supply Voltage Supply Current Shutdown Supply SHDN, SHDM Threshold Common-Mode Bias Voltage 2 1 Conditions TAMB = -40 to +85C VIN- = VIN+ = VBIAS;TAMB = -40 to +85C SHDN = SHDM = GND Min 2.7 Typ 8 0.05 Max 5.5 10.4 1 0.3 x VCC Unit V mA A V V 0.7 x VCC VCC/2 - 5% VCC/2 VCC/2 + 5% AV = 0dB (AS1703) VIN- = VIN+ = VBIAS AV = 3dB (AS1704) AV = 6dB (AS1705) AV = 0dB (AS1703) Inferred from CMRR AV = 3dB (AS1704) Test AV = 6dB (AS1705) External Gain AS1702 AS1703, AS1704, AS1705 fN = 1kHz VIN- = VIN+ = VBIAS; VRIPPLE = 200mVp-p; RL = 8; CBIAS = 1F THD+N = 1%; fIN = 1kHz f = 217Hz f = 1kHz 0.8 1 1 1 0.2 0.9 1.5 1.5 10 10 15 20 VCC - 0.2 VCC - 0.9 VCC - 1.5 VCC - 1.5 20 VOS Output Offset Voltage mV VIC Common-Mode Input Voltage 3 V RIN CMRR PSRR POUT Input Impedance Common-Mode Rejection Ratio Power Supply Rejection Ratio Output Power 4 15 -64 -79 -73 1.25 1.8 0.06 0.03 1 +145 9 125 3.5 50 k dB dB W % THD+N Total Harmonic Distortion plus Noise 5 tPU tSHDN VPOP Gain Accuracy Thermal Shutdown Threshold Thermal Shutdown Hysteresis Power-up/Enable from Shutdown Time Shutdown Time Turn-Off Transient 6 RL = 8 RL = 4 RL = 4, fIN = 1kHz, POUT = 1.28W, VCC = 5V, AV = 6dB RL = 8, fIN = 1kHz, POUT = 0.9W, VCC = 5V, AV = 6dB AS1703, AS1704, AS1705 2 % C C ms s mV 1. Quiescent power supply current is specified and tested with no load. Quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier. 2. Common-mode bias voltage is the voltage on BIAS and is nominally VCC/2. 3. Guaranteed by design. 4. Guaranteed by design. 5. Measurement bandwidth for THD+N is 22Hz to 22kHz. 6. Peak voltage measured at power-on, power-off, into or out of SHDN. Bandwidth defined by A-weighted filters, inputs at AC GND. VCC rise and fall times 1ms. www.austriamicrosystems.com Revision 1.47 4 - 20 AS1702 - AS1705 Data Sheet - E l e c t r i c a l Characteristics 3V Operation Table 5. Electrical Characteristics - 3V Supply, TAMB = +25C (unless otherwise specified) Symbol ICC ISHDN VIH VIL VBIAS Parameter Supply Current 1 Conditions VIN- = VIN+ = VBIAS; TAMB = -40 to +85C, per amplifier SHDN = SHDM = GND per amplifier Min Typ 7.5 0.05 Max Unit mA Shutdown Supply SHDN, SHDM Threshold Common-Mode Bias Voltage 2 1 0.3 x VCC A V V 0.7 x VCC VCC/2 5% AV = 0dB (AS1703) VIN- = VIN+ = VBIAS AV = 3dB (AS1704) AV = 6dB (AS1705) AV = 0dB (AS1703) 0.2 0.6 1.0 1.0 10 15 -64 f = 217Hz f = 1kHz -79 -73 640 440 0.06 0.04 1 +145 9 125 3.5 6 VCC/2 VCC/2 + 5% 1 1 1 10 15 20 VCC - 0.2 VCC - 0.6 VCC - 1.0 VCC - 1.0 20 VOS Output Offset Voltage mV VIC Common-Mode Input Voltage 3 Inferred from CMRR Test AV = 3dB (AS1704) AV = 6dB (AS1705) mV External gain AS1702 RIN CMRR PSRR POUT Input Impedance Common-Mode Rejection Ratio Power Supply Rejection Ratio Output Power 4 AS1703, AS1704, AS1705 fN = 1kHz VIN- = VIN+ = VBIAS; VRIPPLE = 200mVp-p; RL = 8; CBIAS = 1F k dB dB mW RL = 4, THD+N = 1%; fIN = 1kHz RL = 8, THD+N = 1%; fIN = 1kHz RL = 4, fIN = 1kHz, POUT = 460mW, AV = 6dB RL = 8, fIN = 1kHz, POUT = 330mW, AV = 6dB AS1703, AS1704, AS1705 THD+N Total Harmonic Distortion plus Noise 5 % 2 % C C ms s mV Gain Accuracy Thermal Shutdown Threshold Thermal Shutdown Hysteresis tPU tSHDN VPOP Power-up/Enable from Shutdown Time Shutdown Time Turn-Off Transient 50 1. Quiescent power supply current is specified and tested with no load. Quiescent power supply current depends on the offset voltage when a practical load is connected to the amplifier. Guaranteed by design. 2. Common-mode bias voltage is the voltage on BIAS and is nominally VCC/2. 3. Guaranteed by design. 4. Guaranteed by design. 5. Measurement bandwidth for THD+N is 22Hz to 22kHz. 6. Peak voltage measured at power-on, power-off, into or out of SHDN. Bandwidth defined by A-weighted filters, inputs at AC GND. VCC rise and fall times 1ms. www.austriamicrosystems.com Revision 1.47 5 - 20 AS1702 - AS1705 Data Sheet - Ty p i c a l Operating Characteristics 7 Typical Operating Characteristics Figure 3. THD + Noise vs. Frequency; VDD = 3V, RL = 4, AV = 2 10 Figure 4. THD + Noise vs. Frequency; VDD = 3V, RL = 8, Av = 2 10 1 THD + N (%) e 0.1 POUT = 50mW POUT = 250mW THD + N (%) e 1 0.1 POUT = 100mW POUT = 250mW 0.01 0.01 0.001 10 100 1000 10000 0.001 10 100 1000 10000 Frequency (Hz) Figure 5. THD + Noise vs. Frequency; VDD =5V, RL = 4, Av = 2 10 Frequency (Hz) Figure 6. THD + Noise vs. Frequency; VDD = 5V, RL = 8, Av = 2 10 1 1 THD + N (%) e 0.1 POUT = 250mW POUT = 1W THD + N [%] 0.1 POUT = 250mW POUT = 750mW 0.01 0.01 0.001 10 100 1000 10000 0.001 10 100 1000 10000 Frequency (Hz) Figure 7. THD + Noise vs. Frequency; VDD = 5V, RL = 4, Av = 4 10 Frequency [Hz] Figure 8. THD + Noise vs. Output Power; VDD = 5V, RL = 8, Av = 4 10 1 1 POUT = 200mW THD + N (%) e THD + N (%) e 0.1 POUT = 1W 0.1 POUT = 200mW POUT = 800mW 0.01 0.01 0.001 10 100 1000 10000 0.001 10 100 1000 10000 Frequency (Hz) Frequenzy (Hz) www.austriamicrosystems.com Revision 1.47 6 - 20 AS1702 - AS1705 Data Sheet - Ty p i c a l Operating Characteristics Figure 9. THD + Noise vs. Output Power; VDD = 3V, RL = 4, Av = 2 10 Figure 10. THD + Noise vs. Output Power; VDD = 3V, RL = 8, Av = 2 10 THD+N (%) . 1 THD+N (%) . 1 0.1 fIN = 1kHz 0.1 fIN = 1kHz fIN = 100Hz fIN = 100Hz 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 Output Power (W) Output Power (W) Figure 11. THD + Noise vs. Output Power; VDD = 3V, RL = 4, Av = 4 10 Figure 12. THD + Noise vs. Output Power; VDD = 3V, RL = 8, Av = 4 10 THD+N (%) . 1 THD+N (%) . 1 fIN = 1kHz 0.1 fIN = 100Hz 0.1 fIN = 1kHz fIN = 100Hz 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 Output Power (W) Output Power (W) Figure 13. THD + Noise vs. Output Power; VDD = 5V, RL = 4, Av = 2 10 Figure 14. THD + Noise vs. Output Power; VDD = 5V, RL = 8, Av = 2 10 THD+N (%) . 1 THD+N (%) . 1 0.1 fIN = 1kHz 0.1 fIN = 1kHz fIN = 100Hz 0.01 0 0.4 0.8 1.2 1.6 2 0.01 0 0.2 0.4 0.6 0.8 fIN = 100Hz 1 1.2 1.4 1.6 Output Power (W) Output Power (W) www.austriamicrosystems.com Revision 1.47 7 - 20 AS1702 - AS1705 Data Sheet - Ty p i c a l Operating Characteristics Figure 15. THD + Noise vs. Output Power; VDD = 5V, RL = 4, Av = 4 10 Figure 16. THD + Noise vs. Output Power; VDD = 5V, RL = 8, Av = 4 10 THD+N (%) . 1 THD+N (%) . 1 0.1 fIN = 1kHz 0.1 fIN = 1kHz fIN = 100Hz fIN = 100Hz 0.01 0 0.4 0.8 1.2 1.6 2 0.01 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Output Power (W) Output Power (W) Figure 17. Output Power vs. Load Resistance; VDD = 3V 900 800 Figure 18. Output Power vs. Load Resistance; VDD = 5V 2.4 2 POUT @ THD = 10% Output Power (W) e POUT @ THD = 10% Output Power (W) e 700 600 500 400 300 200 100 0 1 10 100 POUT @ THD = 1% 1.6 1.2 0.8 0.4 0 1 10 100 POUT @ THD = 1% Load Resistance () Figure 19. Output Power vs. Supply Voltage; RL = 4 3 2.5 Load Resistance () Figure 20. Output Power vs. Supply Voltage; RL = 8 2 1.8 Output Power (W) e Output Power (W) e 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 POUT @ 1% (W) POUT @ 10% (W) 2 POUT @ 10% (W) 1.5 1 0.5 0 2.5 3.5 4.5 5.5 POUT @ 1% (W) 0 2.5 3.5 4.5 5.5 Supply Voltage (V) Supply Voltage (V) www.austriamicrosystems.com Revision 1.47 8 - 20 AS1702 - AS1705 Data Sheet - Ty p i c a l Operating Characteristics Figure 21. Power Dissipation vs. Output Power; VDD = 3V, RL = 4, Av = 2. f = 1kHz 700 Figure 22. Power Dissipation vs. Output Power; VDD = 3V, RL = 8, Av = 2, f = 1kHz 350 Power Dissipation (mW) e Power Dissipation (mW) e 0 100 200 300 400 500 600 700 600 500 400 300 200 100 0 300 250 200 150 100 50 0 0 100 200 300 400 500 Output Power (mW) Figure 23. Power Dissipation vs. Output Power; VDD = 5V, RL = 4, Av = 2. f = 1kHz 1.8 1.6 Output Power (mW) Figure 24. Power Dissipation vs. Output Power; VDD = 5V, RL = 8, Av = 2. f = 1kHz 1.0 Power Dissipation (W) e Power Dissipation (W) e 0.0 0.3 0.6 0.9 1.2 1.5 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Output Power (W) Figure 25. Shutdown Hysteresis Voltage; VDD = 3V Common Mode Bias Voltage (V) e 3 2.5 2 1.5 1 0.5 0 0 1 2 3 Output Power (W) Figure 26. Shutdown Hysteresis Voltage; VDD = 5V Common Mode Bias Voltage (V) e 3 2.5 2 1.5 1 0.5 0 0 1 2 3 Shutdown Voltage (V) Shutdown Voltage (V) www.austriamicrosystems.com Revision 1.47 9 - 20 AS1702 - AS1705 Data Sheet - Ty p i c a l Operating Characteristics Figure 27. Shutdown Current vs. Temperature 10 VDD = 5V Figure 28. Shutdown Current vs. Temperature 0.03 Supply Current (mA) e 8 VDD = 3V Shutdown Current (uA)e 0.02 0.01 VDD = 5V 6 4 0.00 -0.01 -0.02 -0.03 VDD = 3V 2 0 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 Temperature (C) Figure 29. Power Supply Rejection Ratio vs. Frequency 0 -10 -20 Temperature (C) PSRR (dB) e -30 -40 -50 -60 -70 -80 -90 -100 10 100 1000 10000 100000 VDD = 5V VDD = 3V Frequency (Hz) www.austriamicrosystems.com Revision 1.47 10 - 20 AS1702 - AS1705 Data Sheet - D e t a i l e d Description 8 Detailed Description The AS1702 - AS1705 are 1.8W high output-current audio amplifiers (configured as BTL amplifiers), and contain integrated low-power shutdown and click- and pop-suppression circuitry. Two inputs (SHDM and SHDN) allow shutdown mode to be configured as active-high or active-low (see Shutdown Mode on page 11). Each device has either adjustable or fixed gains (0dB, 3dB, 6dB) (see Ordering Information on page 19). Bias The devices operate from a single 2.7 to 5.5V supply and contain an internally generated, common-mode bias voltage of: VCC 2 (EQ 1) referenced to ground. Bias provides click-and-pop suppression and sets the DC bias level for the audio outputs. Select the value of the bias bypass capacitor as described in Section BIAS Capacitor on page 15. Note: Do not connect external loads to BIAS as this can adversely affect overall device performance. Shutdown Mode All devices implement a 100nA, low-power shutdown circuit which reduces quiescent current consumption. As shutdown mode commences, the bias circuitry is automatically disabled, the device outputs go high impedance, and bias is driven to GND. The SHDM input controls the polarity of SHDN: ! ! Drive SHDM high for an active-low SHDN input. Drive SHDM low for an active-high SHDN input. Table 6. Shutdown Mode Selection Configurations SHDM SHDN Mode 0 0 1 1 0 1 0 1 Shutdown Mode Enabled Normal Operation Enabled Normal Operation Enabled Shutdown Mode Enabled Click-and-Pop Suppression During power-up, the device common-mode bias voltage (VBIAS (see page 4)) ramps to the DC bias point. When entering shutdown, the device outputs are driven high impedance to 100k between both outputs minimizing the energy present in the audio band, thus preventing clicks and pops. www.austriamicrosystems.com Revision 1.47 11 - 20 AS1702 - AS1705 Data Sheet - A p p l i c a t i o n Information 9 Application Information Figure 30. AS1702 Typical Application Diagram RF 20k RF 20k 2.7 to 5.5V Supply 10F 9 VCC Inverting Differential Input Non-Inverting Differential Input CIN* 10F RIN 10k AV = 2 2 IN4 - + 10 OUT+ 6 OUT- CIN* 10F RIN 10k IN+ * Optional 5 CBIAS 0.1F BIAS 1 SHDN 3 SHDM Shutdown Control Bias Generator AS1702 7 GND Figure 31. AS1703, AS1704, AS1705 Typical Application Diagram 2.7 to 5.5V Supply 10F 9 VCC R2 AV = 1 AV = 1.41 AV = 2 - + R1 Inverting Differential Input Non-Inverting Differential Input CIN* 10F 2 IN4 R1 10 OUT+ 6 OUT- CIN* 10F IN+ * Optional 5 CBIAS 0.1F BIAS 1 SHDN 3 SHDM Shutdown Control Bias Generator R2 AS1703/ AS1704/ AS1705 7 GND www.austriamicrosystems.com Revision 1.47 12 - 20 AS1702 - AS1705 Data Sheet - A p p l i c a t i o n Information BTL Amplifier All devices are designed to drive loads differentially in a bridge-tied load (BTL) configuration. Figure 32. Bridge Tied Load Configuration +1 VOUT(P-P) 2 x VOUT(P-P) -1 VOUT(P-P) The BTL configuration doubles the output voltage (illustrated in Figure 32) compared to a single-ended amplifier under similar conditions. Thus, the differential gain of the device (AVD) is twice the closed-loop gain of the input amplifier. The effective gain is given by: AVD = 2 x RF RIN (EQ 2) Substituting 2 x VOUT(P-P) for VOUT(P-P) into (EQ 3) and (EQ 4) yields four times the output power due to doubling of the output voltage: VRMS = VOUT(P-P) 22 VRMS RL 2 (EQ 3) POUT = (EQ 4) Since the BTL outputs are biased at mid-supply, there is no net DC voltage across the load. This eliminates the need for the large, expensive, performance degrading DC-blocking capacitors required by single-ended amplifiers. Power Dissipation and Heat Sinking Normally, the devices dissipate a significant amount of power. The maximum power dissipation is given in Table 3 as Continuous Power Dissipation, or it can be calculated by: PDISSPKF(MAX) = TJ(MAX) -TA JA (EQ 5) where TJ(MAX) is +150C, TAMB (see Table 3) is the ambient temperature, and JA is the reciprocal of the derating factor in C/W as specified in Table 3. For example, JA of the TQFN package is +59.2C/W. The increased power delivered by a BTL configuration results in an increase in internal power dissipation versus a single-ended configuration. The maximum internal power dissipation for a given VCC and load is given by: PDISSPKF(MAX) = 2VCC 2 2RL (EQ 6) www.austriamicrosystems.com Revision 1.47 13 - 20 AS1702 - AS1705 Data Sheet - A p p l i c a t i o n Information If the internal power dissipation exceeds the maximum allowed for a given package, power dissipation should be reduced by increasing the ground plane heat-sinking capabilities and increasing the size of the device traces (see Layout and Grounding Considerations on page 15). Additionally, reducing VCC, increasing load impedance, and decreasing ambient temperature can reduce device power dissipation. The integrated thermal-overload protection circuitry limits the total device power dissipation. Note that if the junction temperature is +145C, the integrated thermal-overload protection circuitry will disable the amplifier output stage. If the junction temperature is reduced by 9, the amplifiers will be re-enabled. Note: A pulsing output under continuous thermal overload results as the device heats and cools. Fixed Differential Gain (AS1703, AS1704, and AS1705) The AS1703, AS1704, and AS1705 contain different internally-fixed gains (see Ordering Information on page 19). A fixed gain facilitates simplified designs, decreased footprint size, and elimination of external gain-setting resistors. The fixed gain values are achieved using resistors R1 and R2 (see Figure 31 on page 12). Adjustable Differential Gain (AS1702) Gain-Setting Resistors The AS1702 uses external feedback resistors, RF and RIN (Figure 33), to set the gain of the device as: AV = RF RIN (EQ 7) where AV is the desired voltage gain. For example, RIN = 10k, RF = 20k yields a gain of 2V/V, or 6dB. Note: RF can be either fixed or variable, allowing the gain to be controlled by software (using a AS150x digital potentiometer. For more information on the AS1500 family of digital potentiometers, refer to the latest version of the AS150x data sheet, available from the austriamicrosystems website http://www.austriamicrosystems.com.) Figure 33. Setting the AS1702 Gain RF 20k RF 20k Inverting Differential Input Non-Inverting Differential Input CIN* 10F RIN 10k 2 IN4 - + 10 OUT+ 6 OUT- CIN* 10F * Optional RIN 10k IN+ 5 BIAS Bias Generator CBIAS 0.1F AS1702 www.austriamicrosystems.com Revision 1.47 14 - 20 AS1702 - AS1705 Data Sheet - A p p l i c a t i o n Information Input Filter The BTL inputs can be biased at voltages other than mid-supply. However, the integrated common-mode feedback circuit adjusts for input bias, ensuring the outputs are still biased at mid-supply. Input capacitors are not required if the common-mode input voltage (VIC) is within the range specified in Table 4 and Table 5. Input capacitor CIN (if used), in conjunction with RIN, forms a high-pass filter that removes the DC bias from an incoming signal. The AC coupling capacitor allows the amplifier to bias the signal to an optimum DC level. Assuming zerosource impedance, the -3dB point of the high-pass filter is given by: f-3dB = 1 2RINCIN (EQ 8) Setting f-3dB too high affects the low-frequency response of the amplifier. Capacitors with dielectrics that have low-voltage coefficients such as tantalum or aluminum electrolytic should be used, since capacitors with high-voltage coefficients, such as ceramics, can increase distortion at low frequencies. BIAS Capacitor BIAS is the output of the internally generated VCC/2 bias voltage. The BIAS bypass capacitor, CBIAS, improves PSRR and THD+N by reducing power supply noise and other noise sources at the common-mode bias node, and also generates the click- and pop-less DC bias waveform for the amplifiers. Bypass BIAS with a 0.1F capacitor to GND. Larger values of CBIAS (up to 1F) improve PSRR, but increase tON/tOFF times. For example, a 1F CBIAS capacitor increases tON/tOFF by 10 and improves PSRR by 20dB (at 1kHz). Note: Do not connect external loads to BIAS. Supply Bypassing Proper power supply bypassing - connect a 10F ceramic capacitor (CBIAS) from VCC to GND - will ensure low-noise, low-distortion performance of the device. Additional bulk capacitance can be added as required. Note: Place CBIAS as close to the device as possible. Layout and Grounding Considerations Well designed PC board layout is essential for optimizing device performance. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance and route heat away from the device. Good grounding improves audio performance and prevents digital switching noise from coupling onto the audio signal. www.austriamicrosystems.com Revision 1.47 15 - 20 AS1702 - AS1705 Data Sheet - P a c k a g e Drawings and Markings 10 Package Drawings and Markings Figure 34. 10-pin MSOP Package Symbol A A1 A2 D D2 E E1 E2 E3 E4 R R1 t1 t2 Typ 1.10 0.10 0.86 3.00 2.95 4.90 3.00 2.95 0.51 0.51 0.15 0.15 0.31 0.41 Tol Max 0.05 0.08 0.10 0.10 0.15 0.10 0.10 0.13 0.13 +0.15/-0.08 +0.15/-0.08 0.08 0.08 Symbol b b1 c c1 1 2 3 L L1 aaa bbb ccc e S Typ 0.23 0.20 0.18 0.15 3.0 12.0 12.0 0.55 0.95BSC 0.10 0.08 0.25 0.50 BSC 0.50 BSC Tol +0.07/-0.08 0.05 0.05 +0.03/-0.02 3.0 3.0 3.0 0.15 - www.austriamicrosystems.com Revision 1.47 16 - 20 AS1702 - AS1705 Data Sheet - P a c k a g e Drawings and Markings Notes: 1. 2. 3. 4. 5. 6. 7. All dimensions are in millimeters (angle in degrees), unless otherwise specified. Datums B and C to be determined at datum plane H. Dimensions D and E1 are to be determined at datum plane H. Dimensions D2 and E2 are for top package and D and E1 are for bottom package. Cross section A-A to be determined at 0.12 to 0.25mm from the lead tip. Dimensions D and D2 do not include mold flash, protrusion, or gate burrs. Dimension E1 and E2 do not include interlead flash or protrusion. www.austriamicrosystems.com Revision 1.47 17 - 20 AS1702 - AS1705 Data Sheet - P a c k a g e Drawings and Markings Figure 35. 10-pin DFN Package (3.0x3.0mm) D D/2 -B- SEE DETAIL B PIN 1 MARKER -A- D2 D2/2 E/2 NXL E2/2 E2 NXK N N-1 e 6 (ND-1) X e BOTTOM VIEW aaa C 2x E INDEX AREA (D/2 xE/2) 4 10 NXb 5 CAB INDEX AREA (D/2 xE/2) 4 aaa C 2x TOP VIEW bbb ddd C 7 8 10 NX ccc C 0.08 C A SIDE VIEW A1 A3 SEATING PLANE -C- D Datum A or B L1 E e Terminal Tip DETAIL B 5 TYPE A ODD TERMINAL SIDE Symbol A A1 A3 L1 L2 K K2 b e aaa bbb ccc ddd eee ggg Min 0.80 0.00 Typ 0.90 0.02 0.20 REF Max 1.00 0.05 0 0.20 0.17 0.18 0.15 0.13 14 0.25 0.5 0.15 0.10 0.10 0.05 0.08 0.10 0.30 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 5 Symbol D BSC E BSC D2 E2 L N ND Min Variations Typ 3.00 3.00 L2 Max 2.20 1.40 0.30 0.40 10 5 2.70 1.75 0.50 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 5 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 www.austriamicrosystems.com Revision 1.47 18 - 20 AS1702 - AS1705 Data Sheet - O r d e r i n g Information 11 Ordering Information The devices are available as the standard products shown in Table 7. Table 7. Ordering Information Model Description AS1702-T AS1703-T AS1704-T AS1705-T AS1702V-T AS1703V-T AS1704V-T AS1705V-T 1.8W Single-Channel Audio Power Amplifier Gain Adjustable Package Type Delivery Form AV = 0dB AV = 3dB AV = 6dB Adjustable AV = 0dB AV = 3dB AV = 6dB 10-pin MSOP, 3x3x0.8mm Tape and Reel 10-pin DFN, 3x3x0.8mm Tape and Reel www.austriamicrosystems.com Revision 1.47 19 - 20 AS1702 - AS1705 Data Sheet Copyrights Copyright (c) 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.47 20 - 20 |
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